This course covers the use of Verilog HDL in high-level synthesis of digital system designs. The language Verilog HDL as well as how it is used for describing, modeling, simulating and synthesizing various digital modules will be addressed. Verilog HDL coding and synthesis issues on combinational and sequential modules including Finite State Machine will be discussed. In the hands-on sessions, the participants will not only learn the language through hands-on coding, synthesis and simulation of some practical designs, but they will also synthesize and test the designs with industrial software packages and FPGA devices.
- Introduction to FPGA/CPLD Software and Hardware Design
- Verilog HDL Design Part 1
- Verilog HDL Design Part 2
- FPGA/CPLD Software and Hardware Development Platform Part 1
- FPGA/CPLD Software and Hardware Development Platform Part 2
- Experiment and Design Project